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2 Commits
77c0ae880d ... b8f0d2dfb2

Author SHA1 Message Date
Sergio Alvariño b8f0d2dfb2 dev: Add some schematics for APC captured on the net
12 months ago
Sergio Alvariño 7fe0f27e53 dev: Add new Atari Punk Console with LFO
12 months ago
13 changed files with 8065 additions and 4280 deletions
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atari_punk_console/kicad/atari_punk_console/atari_punk_console_VCO.kicad_sch
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atari_punk_console/kicad/atari_punk_console_vco/atari_punk_console_vco.kicad_pcb
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(kicad_pcb (version 20221018) (generator pcbnew)
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atari_punk_console/kicad/atari_punk_console_vco/atari_punk_console_vco.kicad_prl
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@ -84,20 +65,26 @@
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"connection_width": "warning",
"copper_edge_clearance": "error", "copper_edge_clearance": "error",
"copper_sliver": "warning",
"courtyards_overlap": "error", "courtyards_overlap": "error",
"diff_pair_gap_out_of_range": "error", "diff_pair_gap_out_of_range": "error",
"diff_pair_uncoupled_length_too_long": "error", "diff_pair_uncoupled_length_too_long": "error",
"drill_out_of_range": "error", "drill_out_of_range": "error",
"duplicate_footprints": "warning", "duplicate_footprints": "warning",
"extra_footprint": "warning", "extra_footprint": "warning",
"footprint": "error",
"footprint_type_mismatch": "error", "footprint_type_mismatch": "error",
"hole_clearance": "error", "hole_clearance": "error",
"hole_near_hole": "error", "hole_near_hole": "error",
"invalid_outline": "error", "invalid_outline": "error",
"isolated_copper": "warning",
"item_on_disabled_layer": "error", "item_on_disabled_layer": "error",
"items_not_allowed": "error", "items_not_allowed": "error",
"length_out_of_range": "error", "length_out_of_range": "error",
"lib_footprint_issues": "warning",
"lib_footprint_mismatch": "warning",
"malformed_courtyard": "error", "malformed_courtyard": "error",
"microvia_drill_out_of_range": "error", "microvia_drill_out_of_range": "error",
"missing_courtyard": "ignore", "missing_courtyard": "ignore",
@ -107,9 +94,14 @@
"padstack": "error", "padstack": "error",
"pth_inside_courtyard": "ignore", "pth_inside_courtyard": "ignore",
"shorting_items": "error", "shorting_items": "error",
"silk_edge_clearance": "warning",
"silk_over_copper": "warning", "silk_over_copper": "warning",
"silk_overlap": "warning", "silk_overlap": "warning",
"skew_out_of_range": "error", "skew_out_of_range": "error",
"solder_mask_bridge": "error",
"starved_thermal": "error",
"text_height": "warning",
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@ -118,7 +110,6 @@
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"via_dangling": "warning", "via_dangling": "warning",
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"min_text_height": 0.7999999999999999,
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@ -156,7 +192,8 @@
"zones_allow_external_fillets": false, "zones_allow_external_fillets": false,
"zones_use_no_outline": true "zones_use_no_outline": true
}, },
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}, },
"boards": [], "boards": [],
"cvpcb": { "cvpcb": {
@ -340,18 +377,23 @@
"rule_severities": { "rule_severities": {
"bus_definition_conflict": "error", "bus_definition_conflict": "error",
"bus_entry_needed": "error", "bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error", "bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error", "bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error", "different_unit_footprint": "error",
"different_unit_net": "error", "different_unit_net": "error",
"duplicate_reference": "error", "duplicate_reference": "error",
"duplicate_sheet_names": "error", "duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error", "extra_units": "error",
"global_label_dangling": "warning", "global_label_dangling": "warning",
"hier_label_mismatch": "error", "hier_label_mismatch": "error",
"label_dangling": "error", "label_dangling": "error",
"lib_symbol_issues": "warning", "lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning", "multiple_net_names": "warning",
"net_not_bus_member": "warning", "net_not_bus_member": "warning",
"no_connect_connected": "warning", "no_connect_connected": "warning",
@ -361,6 +403,7 @@
"pin_to_pin": "error", "pin_to_pin": "error",
"power_pin_not_driven": "error", "power_pin_not_driven": "error",
"similar_labels": "warning", "similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error", "unannotated": "error",
"unit_value_mismatch": "error", "unit_value_mismatch": "error",
"unresolved_variable": "error", "unresolved_variable": "error",
@ -378,7 +421,7 @@
"net_settings": { "net_settings": {
"classes": [ "classes": [
{ {
"bus_width": 12.0, "bus_width": 12,
"clearance": 0.2, "clearance": 0.2,
"diff_pair_gap": 0.25, "diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25, "diff_pair_via_gap": 0.25,
@ -392,13 +435,15 @@
"track_width": 0.25, "track_width": 0.25,
"via_diameter": 0.8, "via_diameter": 0.8,
"via_drill": 0.4, "via_drill": 0.4,
"wire_width": 6.0 "wire_width": 6
} }
], ],
"meta": { "meta": {
"version": 2 "version": 3
}, },
"net_colors": null "net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
}, },
"pcbnew": { "pcbnew": {
"last_paths": { "last_paths": {
@ -414,6 +459,8 @@
"schematic": { "schematic": {
"annotate_start_num": 0, "annotate_start_num": 0,
"drawing": { "drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0, "default_line_thickness": 6.0,
"default_text_size": 50.0, "default_text_size": 50.0,
"field_names": [], "field_names": [],
@ -445,7 +492,11 @@
"page_layout_descr_file": "", "page_layout_descr_file": "",
"plot_directory": "", "plot_directory": "",
"spice_adjust_passive_values": false, "spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"", "spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65, "subpart_first_id": 65,
"subpart_id_separator": 0 "subpart_id_separator": 0
}, },

5110
mfos_noise_toaster/kicad/mfos_noise_toaster/mfos_noise_toaster.kicad_sch
View File

File diff suppressed because it is too large Load Diff

2432
mfos_noise_toaster/kicad/mfos_noise_toaster/mfos_noise_toaster_2.kicad_sch
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File diff suppressed because it is too large Load Diff

2
mfos_wsg/kicad/mfos_wsg/mfos_wsg.kicad_prl
Unescape View File

@ -3,10 +3,12 @@
"active_layer": 0, "active_layer": 0,
"active_layer_preset": "", "active_layer_preset": "",
"auto_track_width": true, "auto_track_width": true,
"hidden_netclasses": [],
"hidden_nets": [], "hidden_nets": [],
"high_contrast_mode": 0, "high_contrast_mode": 0,
"net_color_mode": 1, "net_color_mode": 1,
"opacity": { "opacity": {
"images": 0.6,
"pads": 1.0, "pads": 1.0,
"tracks": 1.0, "tracks": 1.0,
"vias": 1.0, "vias": 1.0,

28
mfos_wsg/kicad/mfos_wsg/mfos_wsg.kicad_pro
Unescape View File

@ -1,5 +1,6 @@
{ {
"board": { "board": {
"3dviewports": [],
"design_settings": { "design_settings": {
"defaults": { "defaults": {
"board_outline_line_width": 0.1, "board_outline_line_width": 0.1,
@ -23,7 +24,8 @@
"track_widths": [], "track_widths": [],
"via_dimensions": [] "via_dimensions": []
}, },
"layer_presets": [] "layer_presets": [],
"viewports": []
}, },
"boards": [], "boards": [],
"cvpcb": { "cvpcb": {
@ -207,18 +209,23 @@
"rule_severities": { "rule_severities": {
"bus_definition_conflict": "error", "bus_definition_conflict": "error",
"bus_entry_needed": "error", "bus_entry_needed": "error",
"bus_label_syntax": "error",
"bus_to_bus_conflict": "error", "bus_to_bus_conflict": "error",
"bus_to_net_conflict": "error", "bus_to_net_conflict": "error",
"conflicting_netclasses": "error",
"different_unit_footprint": "error", "different_unit_footprint": "error",
"different_unit_net": "error", "different_unit_net": "error",
"duplicate_reference": "error", "duplicate_reference": "error",
"duplicate_sheet_names": "error", "duplicate_sheet_names": "error",
"endpoint_off_grid": "warning",
"extra_units": "error", "extra_units": "error",
"global_label_dangling": "warning", "global_label_dangling": "warning",
"hier_label_mismatch": "error", "hier_label_mismatch": "error",
"label_dangling": "error", "label_dangling": "error",
"lib_symbol_issues": "warning", "lib_symbol_issues": "warning",
"missing_bidi_pin": "warning",
"missing_input_pin": "warning",
"missing_power_pin": "error",
"missing_unit": "warning",
"multiple_net_names": "warning", "multiple_net_names": "warning",
"net_not_bus_member": "warning", "net_not_bus_member": "warning",
"no_connect_connected": "warning", "no_connect_connected": "warning",
@ -228,6 +235,7 @@
"pin_to_pin": "warning", "pin_to_pin": "warning",
"power_pin_not_driven": "error", "power_pin_not_driven": "error",
"similar_labels": "warning", "similar_labels": "warning",
"simulation_model_issue": "ignore",
"unannotated": "error", "unannotated": "error",
"unit_value_mismatch": "error", "unit_value_mismatch": "error",
"unresolved_variable": "error", "unresolved_variable": "error",
@ -245,7 +253,7 @@
"net_settings": { "net_settings": {
"classes": [ "classes": [
{ {
"bus_width": 12.0, "bus_width": 12,
"clearance": 0.2, "clearance": 0.2,
"diff_pair_gap": 0.25, "diff_pair_gap": 0.25,
"diff_pair_via_gap": 0.25, "diff_pair_via_gap": 0.25,
@ -259,13 +267,15 @@
"track_width": 0.25, "track_width": 0.25,
"via_diameter": 0.8, "via_diameter": 0.8,
"via_drill": 0.4, "via_drill": 0.4,
"wire_width": 6.0 "wire_width": 6
} }
], ],
"meta": { "meta": {
"version": 2 "version": 3
}, },
"net_colors": null "net_colors": null,
"netclass_assignments": null,
"netclass_patterns": []
}, },
"pcbnew": { "pcbnew": {
"last_paths": { "last_paths": {
@ -281,6 +291,8 @@
"schematic": { "schematic": {
"annotate_start_num": 0, "annotate_start_num": 0,
"drawing": { "drawing": {
"dashed_lines_dash_length_ratio": 12.0,
"dashed_lines_gap_length_ratio": 3.0,
"default_line_thickness": 6.0, "default_line_thickness": 6.0,
"default_text_size": 50.0, "default_text_size": 50.0,
"field_names": [], "field_names": [],
@ -312,7 +324,11 @@
"page_layout_descr_file": "", "page_layout_descr_file": "",
"plot_directory": "", "plot_directory": "",
"spice_adjust_passive_values": false, "spice_adjust_passive_values": false,
"spice_current_sheet_as_root": false,
"spice_external_command": "spice \"%I\"", "spice_external_command": "spice \"%I\"",
"spice_model_current_sheet_as_root": true,
"spice_save_all_currents": false,
"spice_save_all_voltages": false,
"subpart_first_id": 65, "subpart_first_id": 65,
"subpart_id_separator": 0 "subpart_id_separator": 0
}, },

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